Microchip SY88773V Bedienungsanleitung
Microchip
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SY88773V
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DESCRIPTION
Rev.: A Amendment: /0
Issue Date: May 2004
FEATURES
The SY88773V features:
■Multirate up to 3.2Gbps operation
■Wide gain-bandwidth product
■Low-noise 50 Ω CML data outputs
■Chatter-free Loss-of-Signal (LOS) output
■Programmable LOS sensitivity
■On-chip input bias for AC-coupled applications
■TTL /EN input
■Wide power supply and temperature operating
range
The SY88773V evaluation board features:
■AC-coupled I/O with SMA connectors
■Single potentiometer to set LOS LVL
■SMA or test points available to measure non-
critical nodes
AVAILABLE MEASUREMENTS
The SY88773V evaluation board allows the following
measurements:
■Frequency performance
■Output eye pattern generation
■Mask testing
■Jitter
■Output rise/fall time
■BER testing
■Hysteresis measurement
EVALUATION BOARD
The SY88773V low-power limiting post amplifier is designed
for use in fiber-optic receivers. The device connects to typical
transimpedance ampliers (TIAs). The linear signal output
from TIAs can contain significant amounts of noise and may
vary in amplitude over time. The SY88773V quantizes these
signals and outputs typically 800mVppvoltage-limited
waveforms.
The SY88773V operates from a single +3.3V 10% or±
+5V ±10% power supply, over an industrial temperature
range of –40 C to +85 C. With its wide bandwidth and high° °
gain, signals with data rates up to 3.2Gbps and as small as
10mVp-p can be amplified to drive devices with CML or PECL
inputs.
The SY88773V incorporates a loss-of-signal (LOS) open-
collector TTL output with internal 5k pull-up resistor. AΩ
programmable loss-of-signal level set pin (LOSLVL) sets the
sensitivity of the input amplitude detection. LOS asserts
high if the input amplitude falls below the threshold set by
LOSLVL and deasserts low otherwise. LOS can be fed back
to the enable (/EN) input to maintain output stability under a
loss of signal condition. /EN deasserts the true output signal
without removing the input signal. Typically, 4.6dB LOS
hysteresis is provided to prevent chattering.
This manual provides information on the SY88773V
evaluation board. It should be used in conjunction with the
SY88773V data sheet, which contains full specications of
the SY88773V.
The SY88773V evaluation board enables fast and thorough
evaluation of the SY88773V 3.2Gbps CML low-power limiting
post amplier. The board is an easy-to-use, 4-layer high-
speed coplanar design. It is designed to be driven by a high-
speed 3.2Gbps pattern generator.
The SY88773V evaluation board is intended to be
terminated to a 50 scope and provides for simple userΩ
adjustability of the LOS threshold through the adjustment of
an on-board potentiometer. This allows the user to evaluate
various parameters of the SY88773V, as listed in the
“Available Measurements” section of this document.
Figure 1. SY88773V Evaluation Board
3.3V/5V 3.2Gbps CML
LOW-POWER LIMITING POST
AMPLIFIER w/ TTL LOS
SY88773V
EVALUATION BOARD
Layer Definition
1 Signal/GND
2 GND
3 VCC
4 GND
Table 1. SY88773V Evaluation Board Layer Stack-Up
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | SY88773V |
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