Texas Instruments DS160PT801 Bedienungsanleitung

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DS160PT801 PCIe

®

4.0, 16 Gbps, 8-Lane (16-Channel) Retimer

1 Features

•8-lane (16-channel) protocol-aware PCI-express

retimer supporting 16.0, 8.0, 5.0, and 2.5 GT/s

interfaces

•Inter-chip communication (ICC) enable dual chip

link width scaling to form 16-lane Gen-4 retimer

•Supports common clock, separate reference clock

with no spread spectrum clocking (SSC), and

separate reference clock with SSC

•Supports 2x4 bifurcation

•Adaptive receive CTLE and DFE supporting

maximum PCIe Gen-4 channel loss

•Supports equalization training

•Low-latency architecture

•On-chip eye opening monitor (EOM) and PCIe

receive margining capability

•Small 8.50-mm × 13.40-mm BGA package

•Flow-through pinout enables signal breakout in two

signal layers

•Compatible with standard 1.00-mm BGA PCB

manufacturing

•Dual power supply: 1.17 V and 1.8 V

•I2C configuration (up to 1 MHz) through the

external EEPROM or I2C controller

•Industrial temperature range: −40°C to 85°C

2 Applications

•Rack server

•Microserver and tower server

•High performance computing

•Hardware accelerator

3 Description

The DS160PT801 is a high-performance eight-lane

(16-channel) PCI-Express protocol-aware retimer

supporting all standard PCIe data rates up to 16

GT/s. It is used to extend the reach and robustness

of high-speed PCIe serial links, from chip-to-chip

motherboard links to more complex multi-connector

system topologies.

The DS160PT801 supports both common-clock and

independent reference clock architectures, with and

without spread-spectrum clocking. This allows for

maximum flexibility in defining the system clock

architecture.

The eight lanes in the DS160PT801 can be

bifurcated into two x4 links to support different system

topologies.

A compact yet easy-to-manufacture BGA package

provides excellent thermal performance while

enabling optimal placement in space-constrained

applications like 1RU riser cards. This feature reduces

overall solution size, PCB routing complexity, and

BOM cost.

Diagnostic capabilities include in-band receiver

margining, out-of-band non-destructive horizontal

or vertical eye margin monitor, receiver loopback,

encoding error detection, and on die temperature

sensor. These features help gauge link margin and

can be used to monitor system health over time.

The DS160PT801 is configurable through SMBus

interface. The Initial configuration can be

automatically loaded from external EEPROM.

Device Information

(1)

PART NUMBERPACKAGEBODY SIZE (NOM)

DS160PT801FCCSP (332)8.50 mm × 13.40 mm

(1)For all available packages, see the orderable addendum at

the end of the data sheet.

PWR_2B

SMBDAT

SMBCLK

GND

MODE

Address straps

(pull-up, pull-

down, or float)

To system SMBus

1.8 to 3.3 V

REFCLK+

B_PERp0

B_PETp0

B_PERn0

B_PETn0

CDR

B_PERp7

B_PETp7

B_PERn7

B_PETn7

CDR

.

.

.

.

.

.

CDR

A_PETp0

A_PERp0

A_PETn0

A_PERn0

CDR

A_PETp7

A_PERp7

A_PETn7

A_PERn7

.

.

.

.

.

.

REFCLK-

SMB_ADDR_0

SMB_ADDR_1

Multi-level strap

(pull-up, pull-

down, or float)

JTAG_TDO

JTAG_TDI

JTAG_TCK

JTAG_TMS

JTAG_TRST#

From system

JTAG up to 3.3 V

tolerance

PERST#

CLKREQ#

RX_DET_BYP

PWR_2A

PWR_1

Strap or system-

controlled up to

3.3 V tolerance

VDD1.8 V

VDD1.17 V

EE_CLK

EE_DAT

To optional

EEPROM

1.8 to 3.3 V

WIDTH

PRT0_RST#

PRT1_RST#

Strap or system-

controlled up to

1.8 V tolerance

100 MHz100 MHz

REFCLK_OUT+

REFCLK_OUT-

To system JTAG up

to 1.8 V tolerance

PWR_2C

Simplified Schematic

DS160PT801

SNLS592A – DECEMBER 2020 – REVISED JUNE 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Produktspezifikationen