Microchip AT89C51CC01 Bedienungsanleitung
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AT89C51CC01
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Rev. 4129N–CAN–03/08
1
Features
•
80C51 Core Architecture
•
256 Bytes of On-chip RAM
•
1K Bytes of On-chip XRAM
•
32K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Erase/Write Cycle: 100K
•
Boot Code Section with Independent Lock Bits
•
2K Bytes of On-chip Flash for Bootloader
•
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
•
2K Bytes of On-chip EEPROM
Erase/Write Cycle: 100K
•
14-sources 4-level Interrupts
•
Three 16-bit Timers/Counters
•
Full Duplex UART Compatible 80C51
•
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
•
Five Ports: 32 + 2 Digital I/O Lines
•
Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
•
Double Data Pointer
•
21-bit Watchdog Timer (7 Programmable Bits)
•
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
•
Full CAN Controller:
– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:
Each Message Object Programmable on Transmission or Reception
Individual Tag and Mask Filters up to 29-bit Identifier/Channel
8-byte Cyclic Data Register (FIFO)/Message Object
16-bit Status and Control Register/Message Object
16-bit Time-Stamping Register/Message Object
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
Access to Message Object Control and Data Registers Via SFR
Programmable Reception Buffer Length Up To 15 Message Objects
Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
Priority Management for Transmission
Message Object Overrun Interrupt
– Supports:
Time Triggered Communication
Autobaud and Listening Mode
Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz
(1)
Crystal Frequency in X2 Mode
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
•
On-chip Emulation Logic (Enhanced Hook System)
•
Power Saving Modes:
– Idle Mode
– Power-down Mode
1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash Memory
T89C51CC01
AT89C51CC01
2
A/T89C51CC01
4129N–CAN–03/08
•
Power Supply: 3V to 5.5V
•
Temperature Range: Industrial (-40° to +85°C)
•
Packages: VQFP44, PLCC44
Description
The T89C51CC01 is the first member of the CANary
TM
family of 8-bit microcontrollers
dedicated to CAN network applications.
In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory
including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes
EEPROM and 1.2-Kbyte RAM.
Special attention is paid to the reduction of the electro-magnetic emission of
T89C51CC01.
Block Diagram
Notes: 1. 8 analog Inputs/8 Digital I/O
2. 2-Bit I/O Port
Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
UART
CPU
Timer 1
INT1
Ctrl
INT0
C51
CORE
Port 0
P0
Port 1
Port 2
Port 3
Parallel I/O Ports and Ext. Bus
P1(1)
P2
P3
XRAM
1kx8
IB-bus
PCA
RESET
Watch
Dog
PCA
ECI
Vss
Vcc
Timer 2
T2EX
T2
Port 4
P4(2)
10 bit
ADC
Flash
32kx
8
Boot
loader
2kx8
EE
PROM
2kx8
CAN
CONTROLLER
TxDC
RxDC
VAREF
VAVCC
VAGND
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | AT89C51CC01 |
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