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ASIC Test Oriented Simulation Manual

Introduction

A challenge of testing application-specific ICs is creating test patterns by IC-design engineers who do not have deep

knowledge of the test-equipment and the related requirements and restrictions.

This manual bridges the gap by providing explanations, examples, and the necessary information to successfully set

up and perform simulations, which must be usable for testprogram-generation. It also explains the Microchip-internal

transformation-flow and the tools involved.

Terminology

The following terms are used frequently to identify specific test features and constraints:

TerminologyDescription

ATEAutomatic Test Equipment (ATE). A tester is an ATE.

DUTDevice Under Test (DUT)

A hardware product verified on the tester. It can either be a die on a wafer or a

packaged part.

Wafer ProbeTesting operation for die on wafers.

It uses an additional ATE named Prober and a DUT interface named Probe Card.

Final TestTesting operation for packaged parts after assembly.

It uses a DUT interface named Load Board.

Test CycleThe interval of time (also called period) in which a test vector is presented to the DUT.

The beginning of a Test Cycle is the reference time for relative timings.

Test VectorA Test Vector consists of one signal state line in a test pattern.

It contains:

A period that delimits the beginning and end of the test vector, also called Test Cycle.

Signal states. Each signal state is represented by a symbol, which reflects its level and

direction (input or output mode for bidirectional). See Waveform File Format for more

information about symbols.

Timing data. Each signal has its own timing data. Inputs are stimulated at predefined

times (driven by the hardware of the tester), and outputs are sampled at predefined

Strobe times.

Test PatternThis is a set of test vectors, usually composed of one or two files: one for the signal

states and one for the timing information. They are the results from the conversion

of a simulation. The very first test vector starts at time 0, which is the absolute time

(reference) for the pattern.

© 2021 Microchip Technology Inc.

and its subsidiaries

Manual

DS50003170A-page 1

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