Microchip SY88083L Bedienungsanleitung

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SY88083L

1G to 12.5G Limiting Post Amplifier with

Digital Offset Correction

Revision1.0

.

Micrel Inc. • 2180 Fortune Drive • SanJose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

November

8, 2013

Revision 1.0

HBWhelp@micrel.comor (408) 955-1690

General Description

The SY88083Llimiting post amplifier is designed for use in

fiber-optic receivers for continuous mode, multi-rate

applications from 1Gbps to 12.5Gbps.

The SY88083Lcontains a high-bandwidth, high-sensitivity

input stage with user-programmable,wide-range SD

assert/LOS de-assert threshold levels, which enables

optimized system reach. Typically, 4dB of electrical

hysteresis is provided to minimize LOS or SD chattering

caused bynoisy input signals. A logic level control pin is

provided to enableuser selection of an open-collector,

TTL-compatible LOS or SD status indication signal with an

external 5kΩto 10kΩpull-up resistor.

The SY88083Lprovides fasterSD assert and LOS de-

assert times than typical continuous mode devices over

the entire differential input voltage range of 10mV

PP

to

1800mV

PP

.

The SY88083Linput stage also provides a user-selectable

digital offset correction (DOC) function to automatically

compensate for internal device offsets in the high-speed

data path.

The SY88083Lprovides integrated 50Ωinput and output

impedances to optimize the high-speed signal paths and

reduce component count. A TTL-compatible JAM input is

provided to enable a SQUELCH functionby feeding back

the LOS or SD signal. The JAM input disables only the

post amplifier output.

The SY88083Loperates from a single +3.3V power

supply, over temperatures ranging from –40°C to +85°C.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com

.

Features

•Multi-rate operation from 1.0625Gbps to 12.5Gbps

•Selectable digital offset correction for internal offset

compensation in the high-speed data path

•Wide differential input range (10mV

PP

to 1800mV

PP

)

•Wide SD de-assert or LOS assert threshold range

−4.5mV

PP

to 30mV

PP

−4dB typical electrical hysteresis

•Fast SD assert and LOS de-assert times

−1µs typical; 2µs maximum

•Selectable LOS or SD status signal indicator

•TTL-compatible JAM input with internal pull-up

•Low-noise CML data inputs with integrated 50Ω

termination impedance to internal reference V

REF

•Low-noise CML data outputs with integrated 50Ω

termination impedance

−30ps typical rise/fall times

•Wide range power supply: 3.3V ±10%

•Industrial temperature range: −40°C to +85°C

•Available in a tiny 3mm × 3mm QFN package

Applications

•10G/8G Fibre Channel

•10Gigabit Ethernet

•OTN equipment

•SONET OC192; SDH STM64

•WDM/DWDM systems

Markets

•Fibre Channel storage area networks

•Datacom/Enterprise

•High-performance computing

•Telecom

•Wireless base stations

Produktspezifikationen