Microchip SY89542U Bedienungsanleitung
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SY89542U
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Precision Edge
®
SY89542U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
■ Dual 2:1 multiplexer
■ Guaranteed AC performance over temp and voltage:
• DC-to > 3.2Gbps data rate throughput
•< 600ps In-to-Out t
pd
•< 150ps t
r
/t
f
■ Ultra-low jitter design:
•< 1ps
RMS
random jitter
•< 10ps
PP
deterministic jitter
•< 10ps
PP
total jitter (clock)
•< 0.7ps
RMS
crosstalk-induced jitter
■ Unique input isolation design minimizes crosstalk
■ Internal input termination
■ Unique input termination and V
T
pin accepts
DC-Coupled and AC-coupled inputs (LVDS, LVPECL,
CML)
■ 350mV LVDS output swing
■ CMOS/TTL compatible MUX select
■ Power supply 2.5V ±5%
■ –40°C to +85°C temperature range
■ Available in 32-pin (5mm x 5mm) MLF
®
package
FEATURES
2.5V, 3.2Gbps DUAL, DIFFERENTIAL
2:1 LVDS MULTIPLEXER WITH
INTERNAL TERMINATION
Precision Edge
®
SY89542U
APPLICATIONS
■ Redundant clock/data switchover
■ SONET/SDH multi-channel select applications
■ Fibre Channel applications
■ GigE applications
Rev.: D Amendment: /0
Issue Date: August 2007
The SY89542U includes two precision, high-speed 2:1
differential Muxes with LVDS (350mV) compatible outputs
with a guaranteed data rate throughput of 3.2Gbps over
temperature and voltage.
The SY89542U differential inputs include a unique, 3-pin
internal termination that allows access to the termination
network through a V
T
pin. This feature allows the device to
easily interface to different logic standards, both AC- and
DC-coupled without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution.
The SY89542U operates from a single 2.5V supply, and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require a 3.3V supply,
consider the SY89543L. The SY89542U is part of Micrel’s
Precision Edge
®
product family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
Precision Edge
®
LVDS
QA
/QA
INA0
/INA0
V
TA0
50Ω
50Ω
0
MUX A
2:1 MUX
1
INA1
/INA1
V
TA1
50Ω
50Ω
S
SELA (CMOS/TTL)
LVDS
QB
/QB
INB0
/INB0
V
TB0
50Ω
50Ω
0
MUX B
2:1 MUX
1
INB1
/INB1
V
TB1
50Ω
50Ω
S
SELB (CMOS/TTL)
Precision Edge is a registered trademark of Micrel, Inc.
Micro
LeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
2
Precision Edge
®
SY89542U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number Pin Name Pin Function
4, 2, 32, 30, INA0, /INA0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
27, 25, 23, 21 INA1, /INA1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
INB0, /INB0, terminates to a V
T
pin through 50Ω. Note that these inputs will default to an indeterminate
INB1, /INB1 state if left open. Unused differential input pairs can be terminated by connecting one input
to V
CC
and the complementary input to GND through a 1kΩ resistor. The V
T
pin is to be
left open in this configuration. Please refer to the “Input Interface Applications” section for
more details.
3, 31, 26, 22 VTA0 , VTA1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a V
T
VTB0, VTB1 pin. The V
TA0
, V
TA1
, V
TB0
, V
TB1
pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more details.
6, 19 SELA, SELB These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state if left open. Input switching threshold is V
CC
/2.
1, 5, 8, 17, 20, VCC Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors. The 0.01µF
24, 28, 29 capacitor should be as close to V
CC
pin as possible.
10, 11, 14, 15 QA, /QA, Differential Outputs: This differential LVDS output pair provides a copy of the selected
QB, /QB input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs.
Please refer to the “Truth Table” for details. Unused output pairs must be terminated with
100Ω across the differential pair.
7, 9, 12, 13, 16, 18 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane.
Exposed pad
PIN DESCRIPTION
24
23
22
21
20
19
18
17
VCC
INB1
VTB 1
/INB1
VCC
SELB
GND
VCC
VCC
/INA0
VTA0
INA0
VCC
SELA
GND
VCC
1
2
3
4
5
6
7
8
910111213141516
32 31 30 29 28 27 26 25
VCC
VCC
/INA1
VTA1
INA1
INB0
VTB0
/INB0
GND
GND
/QA
QA
GND
QB
/QB
GND
32-Pin MLF
®
Ordering Information
(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89542UMI MLF-32 Industrial SY89542U Sn-Pb
SY89542UMITR
(2)
MLF-32 Industrial SY89542U Sn-Pb
SY89542UMG
(3)
MLF-32 Industrial SY89542U with Pb-Free
Pb-Free bar-line indicator NiPdAu
SY89542UMGTR
(2,3)
MLF-32 Industrial SY89542U with Pb-Free
Pb-Free bar-line indicator NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | SY89542U |
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