Microchip SY89828L Bedienungsanleitung
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SY89828L
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Precision Edge
®
SY89828L
MicreL, Inc.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■ High-performance dual 1:10, 1GHz LVDS fanout
buffer/translator
■ Two banks of 10 differential LVDS outputs
■ Guaranteed AC parameters over temperature and
voltage:
•> 1GHz f
MAX
•< 50ps within device skew
•< 400ps t
r
, t
f
time
■ Each bank includes a 2:1 input mux
■ 2:1 mux input accepts LVDS and LVPECL
■ Low jitter performance
•< 1ps
RMS
cycle-to-cycle jitter
•< 1ps
PP
total jitter
■ 3.3V supply voltage
■ Output enable function
■ LVDS input includes internal 100Ω termination
■ Available in a 64-Pin EPAD-TQFP
FEATURES
3.3V 1GHz DUAL 1:10 PRECISION
LVDS FANOUT BUFFER/
TRANSLATOR WITH 2:1 INPUT MUX
Precision Edge
®
SY89828L
APPLICATIONS
■ Enterprise networking
■ High-end servers
■ Communications
Rev.: D Amendment: /0
Issue Date: January 2008
The SY89828L is a precision fanout buffer with 20
differential LVDS (Low Voltage Differential Swing) output
pairs. The part is designed for use in low voltage 3.3V
applications that require a large number of outputs to drive
precisely aligned, ultra low-skew signals to their destination.
The input is multiplexed from either LVDS or LVPECL (Low
Voltage Positive Emitter Coupled Logic) by the CLK_SEL1
and CLK_SEL2 pins. The Output Enables (OE1 and OE2)
are synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89828L features a low pin-to-pin skew of less
than 50ps—performance previously unachievable in a
standard product having such a high number of outputs.
The SY89828L is available in a single space saving package,
enabling a lower overall cost solution.
TYPICAL APPLICATION CIRCUIT
SEL1
Primary/Backup Clock Select
(Switchover with 2.0ns)
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKB
/LVDS_CLKB
Primary Clock Source
Backup Clock Source
5
5
5
5
100Ω
100Ω
Primary
Card
Redundant
Card
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.
LVPECL inputs not shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
®
2
Precision Edge
®
SY89828L
Micrel, Inc.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Q1
VCCO
/Q6
Q6
/Q5
Q5
/Q4
Q4
/Q3
Q3
/Q2
Q2
/Q1
/Q0
Q0
VCCO
SEL2
LVDS_CLKB
/LVDS_CLKB
VCCI
LVDS_CLKA
/LVDS_CLKA
CLK_SEL1
LVPECL_CLKA
/LVPECL_CLKA
GNDI
OE1
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
OE2
SEL1
GNDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
GNDO
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63
62 61 60 59 58 57
56
55 54 53 52 51 50 49
17 18
19 20 21 22 23 24
25
26 27 28 29 30 31 32
/Q18
VCCO
Q13
/Q13
Q14
/Q14
Q15
/Q15
Q16
/Q16
Q17
/Q17
Q18
Q19
/Q19
VCCO
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
10
10
Q0 – Q9
/Q0 – /Q9
LEN
D
Q
CLK_SEL1
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA
/LVPECL_CLKA
0
1
SEL1
0
1
0
1
CLK_SEL2
LVDS_CLKB
/LVDS_CLKB
LVPECL_CLKB
/LVPECL_CLKB
0
1
100Ω termination
internal
100Ω termination
internal
SEL2
OE1
10
10
Q10 – Q19
/Q10 – /Q19
LEN
D
Q
OE2
Ordering Information
(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89828LHI
(2)
H64-1 Industrial SY89828LHI Sn-Pb
SY89828LHITR
(2)
H64-1 Industrial SY89828LHI Sn-Pb
SY89828LHY
(2)
H64-1 Industrial SY89828LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY89828LHYTR
(2)
H64-1 Industrial SY89828LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Pb-Free package recommended for new designs.
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | SY89828L |
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