Microchip SY89876L Bedienungsanleitung
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SY89876L
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1
Precision Edge
®
SY89876L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Integrated programmable clock divider and 1:2
fanout buffer
Guaranteed AC performance over temperature and
voltage:
• >2.0GHz f
MAX
• <190ps t
r
/t
f
• <15ps within device skew
Low jitter design:
• <10ps
PP
total jitter
• <1ps
RMS
cycle-to-cycle jitter
Unique input termination and VT Pin for DC- and AC-
coupled inputs; CML, PECL, LVDS and HSTL
LVDS-compatible outputs
TTL/CMOS inputs for select and reset
Parallel programming capability
Programmable divider ratios of 1, 2, 4, 8 and 16
Low voltage operation 3.3V
Output disable function
–40°C to 85°C industrial temperature range
Available in 16-pin (3mm x 3mm) MLF
®
package
FEATURES
3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER AND
1:2 FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge
®
SY89876L
APPLICATIONS
SONET/SDH line cards
Transponders
High-end, multiprocessor servers
1
Rev.: E Amendment: /0
Issue Date: August 2007
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
FUNCTIONAL BLOCK DIAGRAM
TYPICAL PERFORMANCE
IN
/IN
S1
(TTL/CMOS)
S0
(TTL/CMOS)
Q1
/Q1
Q0
/Q0
50Ω
50Ω
/RESET
(TTL/CMOS)
V
T
V
REF_AC
S2
(TTL/CMOS)
Divided
by
2, 4, 8
or 16
Enable
MUX
MUX
Enable
FF
Decoder
Divide-by-4
CML/LVPECL/LVDS
622MHz
Clock In
OC-12 to OC-3
Translator/Divider
LVDS
155.5MHz
Clock Out
622MHz In
/
Q0
Q0
/IN
IN
155.5MHz Out
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
2
Precision Edge
®
SY89876L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89876LMI MLF-16 Industrial 876L Sn-Pb
SY89876LMITR
(2)
MLF-16 Industrial 876L Sn-Pb
SY89876LMG
(3)
MLF-16 Industrial 876L with Pb-Free
Pb-Free bar-line indicator NiPdAu
SY89876LMGTR
(2, 3)
MLF-16 Industrial 876L with Pb-Free
Pb-Free bar-line indicator NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number Pin Name Pin Function
12, 9 IN, /IN Differential Input: Internal 50ý termination resistors to V
T
input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
1, 2, 3, 4 Q0, /Q0 Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Q1, /Q1 Unused output pairs must be terminated with 100ý across the different pair.
16, 15, 5 S0, S1, S2 Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V
CC
/2.
6 NC No Connect.
8 /RESET, LVTTL/CMOS Logic Levels: Internal 25ký pull-up resistor. Logic HIGH if left unconnected.
/DISABLE Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is V
CC
/2.
10 VREF-AC Reference Voltage: Equal to V
CC
–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
11 VT Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f “Input Interface Applications” section.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
13 GND, Exposed Ground. Exposed pad must be connected to the same potential as the GND pin.
pad
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
Q0
/
Q0
Q1
/
Q1
IN
VT
VREF-A
C
/IN
S0
S1
VC
C
GN
D
S2
NC
VCC
/
RESET
16-Pin MLF
®
(MLF-16)
/RESET
(1)
S2 S1 S0 Outputs
1 0 X X Reference Clock (pass through)
1 1 0 0 Reference Clock ÷2
1 1 0 1 Reference Clock ÷4
1 1 1 0 Reference Clock ÷8
1 1 1 1 Reference Clock ÷16
0
(1)
X X X Q = LOW, /Q = HIGH
Clock Disable
Note:
1. Reset/Disable function is asserted on the next clock input (IN, /IN)
high-to-low transition.
TRUTH TABLE
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | SY89876L |
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