Supermicro SuperServer 2029P-C1R Bedienungsanleitung

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SuperServer 2029P-C1R/C1RT Quick Reference Guide

JumpeDescriptioDefaultSettinrn g

)lamroN( nepOraelC SOMC1TBJ

)delbanE( 2-1 sniPelbanE oiduA1GPJ

JPLLAN1/LAN2EnablPins 1-2 (Enabled1 e )

)lamroN( 2-1 sniPyrevoceR EM1EMPJ

JPMEManufacturingMode SelecPins 1-2 (Normal2 t )

JVRM1/ JVRMVRM SMB Clock(toBMCorPCHPins 1-2 (BMC,Normal 2 ) )

JWDatch Dogimer EnablPins 1-2 (ResettoSystem1W T e )

Connecto Descriptiorn

tekcos yrettab SOMC draobnO1TB

COM1/COMBackpanel COMport/COMheaderforfrontacces2 s

F FFAN1-6,ANA/ANSystemcooling fanheadersAN1-B (FFAN6,AN A,AN F F B)

IPMI_LANDedicatedIPMI_LAN por t

I-SA0~3,I-SA4~3.0connectionheader supportedbytheIntelPCAT AT7SA AT H

redaeh DEL rewoP1DJ

redaeh lortnoC lenaP tnorF1FJ

JHFI1/JHFIHostFabricInterface (HFI)sidebandheadersfortheHFIcard2 s

JIPMB4-pinBMC External1 I2C )header (foranIPMI-supportedcard

redaeh noisurtnI sissahC1LJ

JM2_M.2slo1 t

JNVI2

C1 INVMe2C rheade

JNVME1/JNVMENVMeSlot1/NVMe Slot2 2

JPI2

C1 IPower Supply SMBbus2C rheade

JPWR1/JPWR8-pinPower Supply connector2 s

JPWR24-pin3 ATX mainpowersupplyconnecto r

JRKRAID Key foronboarddevice1 SA ATs

JSTBYStandbypower heade1 r

JTPMrusted PlatformModule(TPM)/Port80connecto1T r

LAN1/LAN2(NoteGigabitLAN/10G LAN Ethernetportsonthebackpane ) l

S-SA0-S-S3.0connectionHeader supportedbytheIntelSCUAT3ATA

S-SA4/S-SPoweredS-SATATA5 ATA sPortsSuperDOM(Disk OnModule)device

SLOT1/SLOTPCI-Express3.0 X8Slots supportedby3 1CPU

SLOTPCI-Express3.0 X16SlotsupportedbyCPU2 1

SLOT4/SLOT5/SLOTPCI-Express3.0 X16Slots supportedbyCPU6 2

T3 t-SGPIOGeneralPurpose SerialI/Opor

itnedI tinUDIUfier (UID)switc h

USB0/1USB4/Backpanel USB2.0ports(USB0/1)USB 3.0ports(USB4/5 & 5 & )

USB2/Front AccessibleUSB2.0headerforUSB 2/3 3

USBype6T A rUSB 3.0Heade

USB7/Front AccessibleUSB3.0headerforUSB7/88

VGVGPorAA t

3 A.

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 ν

   

   ν

   

   

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   

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 

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 ν

  ν

   ν

  ν

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 ν

 ν

 ν

  

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  ν  

  

  

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 νη  ν

 νη  ν

νη  ν

 νη  ν

 νη  ν

 νη  

 η  ν

 η  ν

 η  

 η  

 η  ν

 η  ν

η   ν

     

  

 

JVRM1

JVRM2

JM2_1

LE3

1

  ν

 ν

M.2-PCH

13

 ν

  

 η  

 η  

Ε ιλά κ

Ε ιλά

   

   κ

  

ν ν  η ιλ 

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ν   η ιλ 

   η ιλ ν

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 

  ν

   λκν

Ε ιλά

 κ Ε ιλά

  

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 η λ 

η    

 η λ

   

Ε ιλά

  ινι ν

  

 η  ν

X11DPi-N(T)

JNVME1JNVME2

JNVI2C1

 

USB2/3

JWD1

T-SGPIO3

SLOT4 SLOT6

SLOT5

SLOT3

SLOT2

SLOT1

LEDM1

JPL1

COM2

JIPMB1

JVRM1

JVRM2

JPME2

USB6

USB7/8

JM2_1

JTPM1

JPME1

JD1

JRK1

LE3

S-S A0-AT3

I-S A0-AT3

I-S A4-AT7

FANB

FANA

JL1

BT1

FAN6

LE1

UID VGA

FAN5

LAN2

LAN1

USB0/1

IPMILA N

USB4/5COM1

JPI2C1

JPWR1

JPWR2

JPWR3

JF1

LE2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

FAN3

FAN4

JSTBY1

S-SATA4

S-SATA5

JNVI2C1 JNVME1

JNVME2

P1-DIMMD2

P1-DIMMD1

P1-DIMME1

P1-DIMMF1

JBT1

FAN1

FAN2

CPU1

CPU2

JPG1

        

JHFI2

JHFI1

JBT1

MNL-1993-QRG Rev. 1.0b

1

RESET

 



2

νλ ν



Front View & Interface

Memory Support

This system supports dual Intel Xeon Scalable-SP or 2nd Gen Intel Xeon Scalable-SP

series processors with support of UltraPath Interconnect (UPI) of up to 10.4 GT/s.

This system supports up to 4TB of 3DS LRDIMM, LRDIMM, 3DS RDIMM, RDIMM, NV-DIMM

DDR4 (288-pin) ECC 2933/2666/2400/2133 MHz memory modules in 16 slots.

Notes:

1. Up to 5TB is supported with (L)RDIMM and DCPMM populated in a balanced memory

configuration.

2. 2933 MHz memory is supported by 2nd Gen Intel Xeon Scalable-SP(82xx/62xx) series

processors only.

3. Unbalanced memory configuration decreases memory performance and is not recommended.

When 1 CPU is used:Memory Population Sequence

1 CPU & 1 DIMMCPU1: P1-DIMMA1

1 CPU & 2 DIMMsCPU1: P1-DIMMA1/P1-DIMMD1

1 CPU & 3 DIMMs CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1

1 CPU & 4 DIMMsCPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1

1 CPU & 5 DIMMs

(Unbalanced: not

recommended)

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1

1 CPU & 6 DIMMCPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/

P1-DIMMF1

1 CPU & 7 DIMMs

(Unbalanced: not

recommended)

CPU1:P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD1/

P1-DIMME1/P1-DIMMF1

1 CPU & 8 DIMMs

(Unbalanced: not

recommended)

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/

P1-DIMMD1/P1-DIMME1/P1-DIMMF1

When 2 CPUs are used:Memory Population Sequence

2 CPUs & 2 DIMMsCPU1: P1-DIMMA1

CPU2: P2-DIMMA1

2 CPUs & 4 DIMMsCPU1: P1-DIMMA1/P1-DIMMD1

CPU2: P2-DIMMA1/P2-DIMMD1

2 CPUs & 6 DIMMsCPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1

CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1

2 CPUs & 8 DIMMsCPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1

CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1

2 CPUs & 10 DIMMs

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/

P1-DIMMF1

CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1

2 CPUs & 12 DIMMs

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/

P1-DIMMF1

CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1/

P2-DIMMF1

2 CPUs & 14 DIMMs

(Unbalanced: not

recommended)

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD1/

P1-DIMME1/P1-DIMMF1

CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMA2/P2-DIMMD1/

P2-DIMME1/P2-DIMMF1

2 CPUs & 16 DIMMs

(Unbalanced: not

recommended)

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/

P1-DIMMD1/P1-DIMME1/P1-DIMMF1

CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMA2/P2-DIMMD2/

P2-DIMMD1/P2-DIMME1/P2-DIMMF1

Memory Population Table

CPU Installation

Caution

:N ODBS ON  O  3 4 SIF N OSDIF 

N BP O NSO SIF IF BS N 

MO TN SN  IO  F 

3 A BN E O DF O  3  P

Attaching the Processor Carrier Assembly to the Heatsink to Form the Processor Heatsink

Module (PHM)

4TS 3O UF 

3 A O DF S

Removing the Dust Cover from

the CPU Socket

Installing the Processor Heatsink Module (PHM)

Remove the dust cover from the CPU socket, exposing the

socket and socket pins as shown on the illustration below.

No: te

Do not touch the socket pins to avoid damaging

them, causing the CPU to malfunction.

Note:Do not use excessive force when tightening the screws to avoid

damaging the LGA lands and the processor.

3A AP EF 4O VN 

V, 3A 51 BN E  TP

1N O SDI 3 O  SIF

3A BN E O SDI 3 O 

SIF O DF O  3P

Processor Carrier Assembly (with CPU mounted

on the Processor Clip)

1

2

3

1O V DB  F  SO

 B SDI O N SO 3A

1O V DB  F  SO

 B SDI O N SO 3A

Processor Carrier Assembly

:N ODBS ON  1 2  SIF N OSDIF 

N BP O NSO SIF IF BS N    EF 

Make sure Mounting

Notches snap into place

A

B

D

C

Printed TriangleSmall Guiding Post

Mounting the Processor Heatsink Module

into the CPU socket (on the motherboard)

6F BS N 

AP  EF 4OVN 

 BN F O N SIF 3A

 BN F O N SIF

O DF O  3BF 

Oval D

Oval C (Large Guiding Post)

12

3

4

3A, 6FBSN  BDBF

AP EF 4O VN 

1N O SDI 2 O  SIF

3A BN E O SDI 2 O 

SIF O DF O  3P

Tighten the screws in the

sequence of 1, 2, 3, 4 (top 3 quarter view)

2

3

2

3

N .

1

1

1N 3A N .

a

b

A

B

d

c

D

C

Socket Pins

F MOUF SIF P BS D P O SF DS UF

DOUF  OM SIF 3 A ODF S

4O NOS SOT DI O C FNE

SIF ODF S P  N

T30 Torx Driver

Use a torque of

12lbf-in

SAFETY INFORMATION

IMPORTANT: See installation instructions and safety warning before connecting

system to power supply.

http://www.supermicro.com/about/policies/safety_information.cfm

WARNING:

To reduce risk of electric shock/damage to equipment, disconnect power from

server by disconnecting all power cords from electrical outlets.

If any CPU socket empty, install protective plastic CPU cap

WARNING:

Always be sure all power supplies for this system have the same power output.

If mixed power supplies are installed, the system will not operate.

For more information go to : http://www.supermicro.com/support

!

!

!

Note:

a) SNK-P0068PSC is for CPU 1 and

SNK-P0068PS is for CPU 2

b) The cut-off section of SNK-P0068PSC

must face towards power supply

 7     3

Produktspezifikationen