Texas Instruments SN74AHC125D Bedienungsanleitung


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1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHC125
,
SN74AHC125
SCLS256L– DECEMBER1995 – REVISEDNOVEMBER2016
SNx4AHC125 Quadruple Bus Buer Gates With 3-State Outputs
1
1 Features
1
•Operating Range: 2 Vto 5.5V
•Latch-UpPerformance Exceeds250 mAPer
JESD 17
•Four IndividualOutput Enable Pins
•All InputsHave Schmitt-TriggerAction
2 Applications
•Flow Meters
•Programmable LogicControllers
•Power OverEthernet (PoE)
•Motor Drivesand Controls
•Electronic Point-of-Sale
3 Description
The SNx4AHC125 devices are quadruple bus buer
gatesfeaturing independentline driverswith3-state
outputs. Each outputis disabled when the associated
output-enable(OE)input ishigh. WhenOE islow, the
respective gate passes the data from the A input to
its Youtput.
To ensure the high-impedance state during power up
or power down,OE must betied to VCC through a
pullup resistor;the minimumvalue of theresistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBERPACKAGE (PINS)BODY SIZE (NOM)
SNx4AHC125FKLCCC (20)8.89 mm 8.89 mm
SNx4AHC125DBSSOP (14)6.20 mm 5.30 mm
SNx4AHC125DSOIC (14)8.65 mm× 3.91 mm
SNx4AHC125NSSO (14)10.30 mm × 5.30 mm
SNx4AHC125WCFP (14)9.21 mm× 5.97 mm
SNx4AHC125DGVTVSOP (14)3.60 mm× 4.40 mm
SNx4AHC125PWTSSOP (14)5.00 mm× 4.40 mm
SNx4AHC125NPDIP (14)19.30 mm × 6.35 mm
SNx4AHC125RGYVQFN (14)3.50 mm× 3.50 mm
SNx4AHC125JCDIP (14)19.56 mm × 6.67 mm
(1)Forallavailablepackages, see theorderable addendum at
the end of the data sheet.
Logic Diagram(Positive Logic)
Pin numbersshown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.

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Modell: SN74AHC125D

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