Microchip SY89827L Bedienungsanleitung
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SY89827L
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Precision Edge
®
SY89827LMicrel, Inc.
M9999-073010
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
■ Dual LVPECL or HSTL input, 10 differential 1.5V
HSTL compatible outputs
■ Congurableasdual-channel10outputorasingle-
channel20outputclockdriver
■ GuaranteedACparametersovertemperatureand
voltage:
• >500MHzf
MAX
• <50pswithindeviceskew
• <1.5nspropagationdelay
• <700pst
r
/ t
f
time
■ Lowjitterdesign
• 186fs
RMS
phasejitter
■ 3.3Vcoresupply,1.8Voutputsupply
■ Output enable function
■ Availableina64-PinEPAD-TQFP
FEATURES
3.3V500MHzDUAL1:10HSTLFANOUT
BUFFER/TRANSLATORWITH2:1MUXINPUT
Precision Edge
®
SY89827L
APPLICATIONS
■ High-performancePCs
■ Workstations
■ Parallelprocessor-basedsystems
■ Otherhigh-performancecomputing
■ Communications
Rev.: F Amendment: /0
Issue Date: July 2010
The SY89827L is a High Performance Bus Clock
Driver with dual 1:10 or single 1:20 HSTL (High Speed
Transceiver Logic) output pairs. The part is designed for
use in low voltage (3.3V/1.8V) applications which require a
large number of outputs to drive precisely aligned, ultra low
skew signals to their destination. The input is multiplexed
from either HSTL or LVPECL (Low Voltage Positive Emitter
Coupled Logic) by the CLK_SEL pin. The Output Enables
(OE1 & OE2) are synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with an
asynchronous control.
The SY89827L features extremely low skew performance
of <50ps over temperature and voltage –performance
previously unachievable in a standard product having such
a high number of outputs. The SY89827L is available in a
single space saving package, enabling a lower overall cost
solution. For applications that require greater HSTL fanout
capability, consider the SY89824L.
TYPICALAPPLICATIONCIRCUIT
SEL1
Primary/Backup Clock Select
(Switchover within 2.0ns)
LVPECL_CLKA
/LVPECL_CLKA
LVPECL_CLKB
/LVPECL_CLKB
PrimaryClockSource
RedundantBackup
ClockSource
10
10
10
10
Primary
Card
Redundant
Card
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.
LVPECL inputs only, shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
®
NOT RECOMMENDED FOR NEW DESIGNS
2
Precision Edge
®
SY89827LMicrel, Inc.
M9999-073010
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONALBLOCKDIAGRAM
0
1
HSTL_CLKA
/HSTL_CLKA
LVPECL_CLKA
/LVPECL_CLKA
HSTL_CLKB
/HSTL_CLKB
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
0
1
SEL2
SEL1
0
1
OE2
OE1
0
1
Q
0
– Q
9
10
10
/Q
0
– /Q
9
Q
10
– Q
19
10
10
/Q
10
– /Q
19
LEN
D
Q
CLK_SEL1
LEN
D
Q
Q1
VCCO
/Q6
Q6
/Q5
Q5
/Q4
Q4
/Q3
Q3
/Q2
Q2
/Q1
/Q0
Q0
VCCO
SEL2
HSTL_CLKB
/HSTL_CLKB
VCCI
HSTL_CLKA
/HSTL_CLKA
CLK_SEL1
LVPECL_CLKA
/
LVPECL_CLKA
GND
OE1
LVPECL_CLKB
/
LVPECL_CLKB
CLK_SEL2
OE2
SEL1
VCCO
Q7
/Q7
Q8
/Q8
Q9
/Q9
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
VCCO
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63
62 61 60 59 58 57
56
55 54 53 52 51 50 49
17 18 19 20 21 22 23 24
25
26 27 28 29 30 31 32
/Q18
VCCO
Q13
/Q13
Q14
/Q14
Q15
/Q15
Q16
/Q16
Q17
/Q17
Q18
Q19
/Q19
VCCO
64-PinTQFP(H64-1)
PACKAGE/ORDERINGINFORMATION
Ordering Information
(1)
Package Operating Package Lead
PartNumber Type Range Marking Finish
SY89827LHI H64-1 Industrial SY89827LHI Sn-Pb
SY89827LHITR
(2)
H64-1 Industrial SY89827LHI Sn-Pb
SY89827LHY
(3)
H64-1 Industrial SY89827LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY89827LHYTR
(2, 3)
H64-1 Industrial SY89827LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
Produktspezifikationen
| Marke: | Microchip |
| Kategorie: | Nicht kategorisiert |
| Modell: | SY89827L |
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