Texas Instruments SN74F125DR Bedienungsanleitung
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SN74F125DR
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SN74F125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS016B – JANUARY 1989 – REVISED JULY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-State Outputs Drive Bus Lines or Buer
Memory Address Registers
description/ordering information
The SN74F125 features independent line drivers
with 3-state outputs. Each output is disabled when
the associated output-enable (OE) input is high.
ORDERING INFORMATION
TAPACKAGE
†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N Tube SN74F125N SN74F125N
SOIC D
Tube SN74F125D
F125
0 C°C to 70°
SOIC
–
D
Tape and reel SN74F125DR
F125
SOP – NS Tape and reel SN74F125NSR 74F125
SSOP – DB Tape and reel SN74F125DBR F125
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buer)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D, DB, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
SN74F125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS016B – – JANUARY 1989 REVISED JULY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
4
5 6
2A 2Y
2OE
1
2 3
1A 1Y
1OE
10
9 8
3A 3Y
3OE
13
12 11
4A 4Y
4OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65 C–°C to 150°. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and”
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not“ ”
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –15 mA
IOL Low-level output current 64 mA
TAOperating free-air temperature 0 70 C°
NOTE 3: All unused inputs of the device must be held at V
CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74F125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SDFS016B – – JANUARY 1989 REVISED JULY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER MIN TYPTEST CONDITIONS †MAX UNIT
VIK VCC = 4.5 V, II = – –18 mA 1.2 V
VCC 4 5 V
IOH = –3 mA 2.4 3.3
VOH
V
CC =
4
.
5
V
IOH = –15 mA 2 3.1 V
VCC = 4.75 V, IOH = –3 mA 2.7
VOL VCC = 4.5 V, IOL = 64 mA 0.4 0.55 V
IIVCC = 0, V
I = 7 V 0.1 mA
IIH VCC = 5.5 V, V
I = 2.7 V 20 Aµ
IIL VCC = 5.5 V, V
I = 0.5 V –20 Aµ
IOZH VCC = 5.5 V, V
O = 2.7 V 50 Aµ
IOZL VCC = 5.5 V, V
O = 0.5 V –50 Aµ
IOS‡VCC = 5.5 V, V
O = 0 – –100 225 mA
ICCH VCC = 5.5 V, Outputs open 17 24 mA
ICCL VCC = 5.5 V, Outputs open 28 40 mA
ICCZ VCC = 5.5 V, Outputs open 25 35 mA
†All typical values are at V
CC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX§UNIT
MIN TYP MAX MIN MAX
tPLH
A
Y
1.2 3.6 6 1.2 6.5
ns
tPHL
A
Y
2.2 5.1 7.5 2.2 8
ns
tPZH
OE
Y
2.7 5.1 7.5 2.7 8.5
ns
tPZL
OE
Y
3.2 5.6 8 3.2 9
ns
tPHZ
OE
Y
1 3.1 5 1 6
ns
tPLZ
OE
Y
1 3.1 5.5 1 6
ns
§For conditions shown as MIN or MAX, use the appropriate value specied under recommended operating conditions.
Produktspezifikationen
| Marke: | Texas Instruments |
| Kategorie: | Nicht kategorisiert |
| Modell: | SN74F125DR |
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